Design of an integrated CMOS operational amplifier with low probability EMI induced failures

In this paper the design of an operational amplifier with enhanced immunity to electromagnetic interference (EMI) conveyed to the input terminals is presented. It has a symmetric topology, based on two main blocks; the first is a fully differential folded cascode and the second is a source cross-coupled AB class buffer. The integrated circuit has been fabricated in a 0.8 µm n-well CMOS technology (AMS CYE process). Its main features are: a gain of 93 dB, the GBW of 10.4 MHz and a symmetric slew rate. The supply voltage can range from 3.3 to 5 V.