An 8 × 8 sub-threshold digital CMOS carry save array multiplier

Digital Sub-threshold logic can be used to achieve very low power consumption in applications where performance is not of primary concern. In this paper we present a robust sub-threshold logic circuit namely Variable Threshold Subthreshold CMOS (VT-Sub-CMOS) logic, which can be operated under different temperature conditions and process variations. Simulation results show that both delay and power-delay-product (PDP) of VT-Sub-CMOS are about 5 times better than normal subthreshold CMOS circuits under such conditions. We also show an 8×8 robust digital sub-threshold CMOS (sub-CMOS) array multiplier. Measured results on TSMC 0.35 µm process technology show excellent subthreshold operation of the multiplier even if the supply voltage (0.47V) is far below the threshold voltage (0.67V) of NMOS transistor. The PDP of the multiplier is about 25 times better than its strong inversion operation.