Design and analysis methodology for a bluetooth sub-micron CMOS PA

This paper presents the methodology to design a Power Amplifier in sub-micron CMOS technology, taking into account all the parasitic effects. A modeling of the bonding distribution, lead frame and board parasites was defined to accurately design such a cell. A radiated electric field characterization was investigated to see the package and metal influence, and to point out propagation issues above a silicon chip. The PA has been integrated in a double oxide 0.18 µm RF CMOS. It delivers 8dBm output power with more than 25% of efficiency at 2.45GHz.