Implementation of an efficient lattice digital ladder filter for up/down conversion in an OFDM-WLAN system

A novel architecture for a lattice digital ladder filter (LDLF) is presented. The design of the proposed filter is based on a low-sensitive bilinear transformation of analogue ladder filters where the delay-free loops are eliminated. The proposed filter is very efficient, as it gives a sharp amplitude response with a small number of multipliers. It also has a low sensitivity to round-off noise, and good stability properties. A 5^thorder elliptic filter has been realized for the digital I/Q up/down conversion stage in an OFDM-based WLAN chip using a 0.35µm CMOS process. The design has a power consumption of 137mW and occupying an area equivalent to 5.6kgates.