Low-power complex polynomial predistorter circuit in CMOS for RF power amplifier linearization

A chip that implements an analog 5th order complex polynomial for linearization of RF power amplifiers is presented. The chip has been designed in a 0.35µm CMOS process and operates at an IF of 200MHz with signal bandwidths of several MHz. The predistorter core consumes 2mA from a 2.7V supply and 11.5mA including the input and output buffers. Experimental results demonstrate that third and fifth-order intermodulation distortion (IMD) can be suppressed by more than 30dB and 5dB, respectively with two-tone test and a class A amplifier in deep saturation. Large reduction of adjacent channel power is also obtained with IS-95 and WCDMA signals.