A 80MHz band-pass Δ Σ-modulator for a 100MHz IF-receiver

A fully differential 4th-order band-pass ΔΣ-modulator is presented. The circuit is targeted for a 100MHz GSM/WCDMA-multi-mode IF-receiver and operates at a sampling frequency of 80MHz. It combines frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 100MHz to a digital intermediate frequency of 20MHz. The modulator is based on a double-delay single-Opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive against different component nonidealities. The measured peak SNR is 78dB and 43.3dB for a 270kHz(GSM) and 3.84MHz(WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35µm CMOS technology and consumes 61.2mW from a 3.0V supply.