A 3.2-mA 6-bit pipelined A/D converter for a bluetoothTM1RF transceiver

A low power consumption 6-bit pipelined analog-to-digital converter for use in a Bluetooth RF transceiver has been developed. The RF transceiver chip was fabricated by using the 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used/developed 1) the look-ahead pipeline architecture to shorten the critical path in the converter and 2) a S/H amplifier with a newly designed switched capacitor common mode feedback for a differential operational-amplifier. Offset compensation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13-Msps and 5.0 at 26- Msps. And it has a low total current consumption of 3.2- mA at 13-Msps and a supply voltage of 2.8-V.