Planar 1T-cell DRAM with MOS storage capacitors in a 130nm logic technology for high density microprocessors caches

IT-cell DRAM arrays with planar MOS capacitors are fabricated in a high performance 130nm logic technology without any process enhancements. Storage capacitors are operated in traditional inversion mode (N+/P), accumulation mode (P+/N) and in depletion mode (P+/P). The P+/P storage cap cell is 3.5X smaller than a 6T SRAM cell and gives a 2X array density advantage over the best SRAM cache design. Measured retention time at 110°C is 350ns with 1W/cm2 refresh power density.