DocumentCode
439725
Title
A 0.13- µm CMOS NOR flash memory experimental chip for 4-b/cell digital storage
Author
Micheloni, R. ; Khouri, O. ; Gregori, S. ; Cabrini, A. ; Campardo, G. ; Fratin, L. ; Torelli, G.
Author_Institution
STMicroelectronics, Agrate Brianza, Italy
fYear
2002
fDate
24-26 Sept. 2002
Firstpage
131
Lastpage
134
Abstract
This paper presents architectural and circuit solutions developed to achieve 4-b/cell storage in NOR-type Flash memories. A multiple closed-loop voltage sensing topology, combined with hierarchical load-decoupling row selection, and a two-step analog-to-digital conversion with early most significant bit (MSB) detection, achieve 120-ns access time for the stored MSBs. 80-mV programming step is provided by a switched-capacitor staircase waveform generator. Experimental data from a 0.13-µm CMOS test-chip are given.
Keywords
Analog-digital conversion; Channel hot electron injection; Circuit testing; Circuit topology; Decoding; Fabrication; Flash memory; Research and development; Signal generators; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location
Florence, Italy
Type
conf
Filename
1471483
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