A 0.5V, 1 µ W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18µm CMOS technology. Neither low-VTdevices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noise-and-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30µW and 0.85µW, respectively. Proper operation is achieved down to a supply voltage of 0.4V.