A 5.2GHz LNA in 0.35 µm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

A current-reused two-stage low noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and suggested guidelines for high gain operation along with supporting measurement results. The proposed LNA is implemented based on a 0.35 µm CMOS technology for 5.2GHz WLAN. Measurements show power gain = 19.3 dB, NF = 2.45 dB, and IP3 = 13.2 dBm, respectively, for the dc power supply of 8mA and 3.3 V.