A 12b 80MSps pipelined ADC core with 190mW consumption from 3V in 0.18 µm digital CMOS

The ADC presented demonstrates the efficiency of the straight 1.5 bit-per-stage pipelined approach up to 12b resolution and 80MSps speed. Performance of 66dB SNR and 75dB SFDR at 80MSps/31MHz input is obtained without calibration, drawing 192mW in the analog core (259mW total) from 3V supply. Same values are achieved at 100MSps when the power is increased to 391mW. The ADC has been fabricated in a purely digital 0.18µm CMOS process, in order to allowing for integration with advanced DSP cores. Still the popular figure of merit considering power-effective resolution-speed, rates this converter´s performance among the best in its class.