A pipelined D/A converter with an improved driving scheme for DMT-signals

This paper presents the design of a pipelined switched-capacitor D/A-converter with a novel driving scheme. This driving scheme is optimized for signals with a high crest factor. Such signals occur in modern communication systems such as DMT-based VDSL. The 0.6 µm CMOS prototype circuit was tested with DMT test signals and achieves 12 effective bits for clock frequencies upto 17.664 MHz. The power consumption of the DAC itself is only 60 mW and an additional 25 mW is consumed by a Track&Hold.