A 14-bit delta-sigma modulator for ADSL-CO applications in 0.18 µm CMOS

A high-resolution multi-bit Sigma-Delta ADC implemented in a 0.18µm CMOS technology is introduced. Active blocks are composed of regular threshold voltage devices only. The circuit is targeted for an ADSL Central - Office (CO) application [3]. An area- and power-efficient realization of a 2nd -order, single-loop, 3-bit modulator with high oversampling ratio (OSR=96) is presented. The ΣΔ - modulator features an 85 dB dynamic range over a 300 kHz signal bandwidth. The measured power consumption of the ADC core is 15 mW only.