Low jitter design of a 0.35 µm-CMOS frequency divider operating up to 3GHz

The design of a 32/33 frequency divider, that can operate with input frequency up to 3GHz is discussed, The circuit is realized in a 0.35µm CMOS technology. Particular attention is devoted to assess, in simple terms, the output phase noise and its reduction due to the adoption of a synchronization flip-flop. The measured noise level, -172 dBc/Hz, matches within 1dB with the value predicted by the theory. The minimum input differential signal is 50 mV zero-peak. The power dissipation is 27mW.