A mixed-mode array processor with polynomial-type couplings

A mixed-mode parallel processor is presented in which the processing units can be coupled with first-, second-and third-order polynomial feedback terms of the state of a processing unit. It combines analog and digital processing so that the realization of couplings and the polynomial terms are implemented with analog blocks whereas integration of cell state is digital and A/D- and D/A converters are used to interface between them. A network with 2*72 processing units with 36 layers of memory in each was manufactured using a 0.25µm digital CMOS process. The network can perform gray scale Heun´s integration for a 72*72 data while keeping all I/O operations local. Experimental results of the chip characteristics are shown.