A new multiplexed electrode-per-bit structure for CCD memory

An advanced form of the multiplexed electrode-per-bit (ME/B) structure is described for CCD memory applications. In the new structure, a merging serial register is combined to an ME/B array to make a practical and flexible CCD array, thus the structure is called as the Merging ME/B (M²E/B). An n-channel two level polysilicon gate structure with ion implanted barriers and offset CCD clocks lead to simple rectangular layout in addition to low power consumption. A 64-kbit CCD memory utilizing the structure was designed and tested. The memory operates typically at data rates of 5 Mbits/sec but 512 bit test array operated in less than 100 nsec transfer execution time.