Implications of pocket optimisation on analog performance in deep sub-micron CMOS

Author

Roes, R.F.M. ; van Brandenburg, A.C.M.C. ; Montree, A.H. ; Woerlee, P.H.

Author_Institution

Philips Research Laboratories, Eindhoven, The Netherlands

Volume

fYear

1999

fDate

13-15 Sept. 1999

Firstpage

176

Lastpage

179

Keywords

CMOS process; CMOS technology; Degradation; Energy consumption; Implants; Leakage current; MOS devices; MOSFETs; Performance gain; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 1999. Proceeding of the 29th European

Conference_Location

Leuven, Belgium

Print_ISBN

2-86332-245-1

Type

Filename

1505468

Link To Document