Efficient Receiver Architecture for LDPC Coded BICM-ID System

The low-density parity-check (LDPC) coded bit-interleaved coded modulation with iterative demapping (BICM-ID) has excellent bit error rate (BER) performance, but with extremely high receiver complexity. This letter proposes a three-stage full-parallel receiver architecture in which each component decoder is separately but simultaneously iteratively decoded. This architecture can make full use of the computing resources and improve the system performance without sacrificing the throughput. Three-dimensional (3-D) extrinsic information transfer (EXIT) analysis and BER simulations are carried out to demonstrate the superiority of the proposed new receiver architecture.