DocumentCode
440292
Title
Silicon Stacked Transistor with Source and Drain Tunnel Barriers
Author
Kisu, Teruaki ; Nakazato, Kazuo
Author_Institution
Hitachi ULSI System, Tokyo, Japan
Volume
1
fYear
1999
fDate
13-15 Sept. 1999
Firstpage
532
Lastpage
535
Keywords
Annealing; Atomic layer deposition; Current measurement; Current-voltage characteristics; Impurities; Laboratories; Silicon compounds; Threshold voltage; Ultra large scale integration; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 1999. Proceeding of the 29th European
Conference_Location
Leuven, Belgium
Print_ISBN
2-86332-245-1
Type
conf
Filename
1505557
Link To Document