A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

Author

Agarwala, B. ; Armacost, M. ; Biesemans, S. ; Burrell, L. ; Chen, B. ; Han, K. ; Harmon, D. ; Heidenreich, J. ; Holloway, K. ; Hook, T. ; Kapur, S. ; Kebede, T. ; Kiesling, D. ; Kim, P. ; Matusiewicz, G. ; Lukaitis, J. ; Nguyen, P. ; Prabhakara, N. ; Rauc

Author_Institution

IBM Microelectronics Division, Hopewell Junction, VT, USA

Volume

fYear

1999

fDate

13-15 Sept. 1999

Firstpage

632

Lastpage

635

Keywords

CMOS logic circuits; CMOS technology; Copper; Doping; Implants; Microelectronics; Random access memory; Space technology; Threshold voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 1999. Proceeding of the 29th European

Conference_Location

Leuven, Belgium

Print_ISBN

2-86332-245-1

Type

Filename

1505582

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