440306

A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

Agarwala, B. ; Armacost, M. ; Biesemans, S. ; Burrell, L. ; Chen, B. ; Han, K. ; Harmon, D. ; Heidenreich, J. ; Holloway, K. ; Hook, T. ; Kapur, S. ; Kebede, T. ; Kiesling, D. ; Kim, P. ; Matusiewicz, G. ; Lukaitis, J. ; Nguyen, P. ; Prabhakara, N. ; Rauc

IBM Microelectronics Division, Hopewell Junction, VT, USA

1

1999

13-15 Sept. 1999

632

635

CMOS logic circuits; CMOS technology; Copper; Doping; Implants; Microelectronics; Random access memory; Space technology; Threshold voltage; Wiring;

English

ieee

Solid-State Device Research Conference, 1999. Proceeding of the 29th European

Leuven, Belgium

2-86332-245-1

conf

1505582