An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique

Author

Park, Yujin ; Hwang, Sanghoon ; Song, Minkyu

Author_Institution

Dept. of Semicond. Sci., Dongguk Univ., Seoul, South Korea

Volume

1

fYear

2005

fDate

28 Aug.-2 Sept. 2005

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a resistor-based offset averaging technique, and a one-zero detecting encoder are proposed. The fabricated chip with 0.1 μm CMOS occupies an area of 977 μm × 1040 μm and consumes 145mW at 1.8V power supply. The measured DNL is within 0.5LSB, and the measured SNDR is about 34.55dB, when the input frequency is 10MHz at 2GHz sampling frequency.

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; interpolation; 0.1 micron; 1.8 V; 10 MHz; 1040 micron; 145 mW; 2 GHz; 6 bit; 977 micron; CMOS analog-to-digital converter; DC reference fluctuation reduction; flash type ADC; high-speed operation; interpolation technique; offset averaging technique; one-zero detecting encoder; Character generation; Error correction codes; Fluctuations; Frequency measurement; Interpolation; Logic circuits; Logic testing; MOSFET circuits; Parasitic capacitance; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on

Print_ISBN

0-7803-9066-0

Type

conf

DOI

10.1109/ECCTD.2005.1522925

Filename

1522925