Dynamic state-retention flip flop for fine-grained sleep-transistor scheme

Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for its state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100ps to 200ps.