A 0.35 μm CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code

Author

Vogrig, D. ; Gerosa, A. ; Neviani, A. ; Amat, A. Graell I ; Montorsi, G. ; Benedetto, S.

Author_Institution

DEI, Univ. di Padova, Italy

Volume

1

fYear

2005

fDate

25-28 July 2005

Firstpage

31

Abstract

In this work, we present the design and preliminary testing results of the first reported CMOS analog turbo decoder for a code of realistic complexity, a parallel concatenated, rate 1/3, code defined in the 3GPP standard with interleaver size of 40 bits and a codeword size of 132 bits. The preliminary test results demonstrated a data rate of 2 Mbit/s, with a power consumption of 6.6 mW (decoder core alone) and an energy per decoded bit and trellis state of only 1.36 nJ. Different short range low power wireless data transmission systems for ISM (Industrial Scientific and Medical) applications are compared with respect to their performances (power consumption, distance range, architecture well suited to integration, etc).

Keywords

3G mobile communication; CMOS analogue integrated circuits; channel coding; concatenated codes; turbo codes; 0.35 micron; 1.36 nJ; 132 bit; 2 Mbit/s; 3GPP standard; 40 bit; 6.6 mW; CMOS analog turbo decoder; UMTS channel code; parallel concatenated code; wireless data transmission systems; 3G mobile communication; AWGN; CMOS technology; Code standards; Concatenated codes; Convolutional codes; Energy consumption; Iterative decoding; Niobium; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics, 2005 PhD

Print_ISBN

0-7803-9345-7

Type

conf

DOI

10.1109/RME.2005.1542996

Filename

1542996