DocumentCode
443249
Title
A regular modular architecture for pipelined binary tree multipliers based on a sog structure
Author
Testoni, Nicola ; Cisterni, Marco ; Franchi, Eleonora
Volume
1
fYear
2005
fDate
25-28 July 2005
Firstpage
66
Lastpage
69
Keywords
Adders; Binary trees; CMOS technology; Circuit simulation; Costs; Delay lines; Field programmable gate arrays; Integrated circuit technology; Pipelines; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN
0-7803-9345-7
Type
conf
DOI
10.1109/RME.2005.1543005
Filename
1543005
Link To Document