• DocumentCode
    443280
  • Title

    HALOTIS - high accurate logic timing simulator

  • Author

    Ruiz-de-Clavijo, P. ; Bellido, M.J. ; Juan, J.

  • Author_Institution
    Dpto. Tecnologia Electronica, Univ. de Sevilla, Spain
  • Volume
    1
  • fYear
    2005
  • fDate
    25-28 July 2005
  • Firstpage
    217
  • Abstract
    This paper present a novel logic-timing simulator that includes the degradation delay model (DDM) called HALOTIS. DDM obtains high accuracy in glitches treatment and it has been included in HALOTIS simulation engine. Also, it is possible to estimate switching activity using it, and the results show a high accuracy in simulations when these are compared to HSPICE.
  • Keywords
    circuit simulation; logic simulation; HALOTIS simulation engine; degradation delay model; high accurate logic timing simulator; switching activity estimation; Circuit simulation; Computational modeling; Degradation; Delay; Distributed decision making; Energy consumption; Engines; Logic; Semiconductor device modeling; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Research in Microelectronics and Electronics, 2005 PhD
  • Print_ISBN
    0-7803-9345-7
  • Type

    conf

  • DOI
    10.1109/RME.2005.1543043
  • Filename
    1543043
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=443280