Title :
Scalability and reliability of TaN/HfN/HfO2 gate stacks fabricated by a high temperature process
Author :
Kang, J.F. ; Yu, H.Y. ; Ren, C. ; Yang, H. ; Sa, N. ; Liu, X.Y. ; Han, R.Q. ; Li, M.-F. ; Chan, D.S.H. ; Kwong, D.-L.
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
The scalability and reliability issues of the CVD-HfO2 gate dielectrics with PVD TaN/HfN electrodes, fabricated by a high temperature process, were addressed. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.75 nm and 0.95 nm for MOS capacitor and MOSFET, respectively. Low preexisting traps in the TaN/HfN/HfO2 gate stacks were observed, which could be attributed to the high temperature post gate annealing process. The excellent reliability characteristics were achieved in the TaN/HfN/HfO2 gate stacks.
Keywords :
CVD coatings; MOS capacitors; MOSFET; annealing; dielectric thin films; hafnium compounds; high-temperature techniques; nanotechnology; reliability; semiconductor device reliability; tantalum compounds; vapour deposition; 0.75 nm; 0.95 nm; CVD; MOS capacitor; MOSFET; PVD; TaN-HfN-HfO2; electrodes; gate dielectrics; high temperature process; post gate annealing process; reliability issues; scalability issues; Annealing; CMOS technology; Fabrication; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOS capacitors; MOSFET circuits; Scalability; Temperature;
Conference_Titel :
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN :
0-7803-9203-5
DOI :
10.1109/ESSDER.2005.1546663
