Impact of Technology Scaling on SRAM Soft Error Rates

Author

Chatterjee, I. ; Narasimham, B. ; Mahatme, N.N. ; Bhuva, B.L. ; Reed, R.A. ; Schrimpf, R.D. ; Wang, J.K. ; Vedula, N. ; Bartz, B. ; Monzel, C.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

Volume

61

Issue

6

fYear

2014

fDate

Dec. 2014

Firstpage

3512

Lastpage

3518

Abstract

Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

Keywords

SRAM chips; radiation hardening (electronics); technology CAD (electronics); 3D TCAD simulations; dual-well SRAM circuits; heavy-ion induced upset cross-section; particle LET; single-event response; single-event upsets; size 28 nm; size 40 nm; size 65 nm; soft error rates; soft-error sensitivity; technology scaling; triple-well SRAM circuits; well-engineering; Doping; Error analysis; Layout; MOSFET; SRAM cells; Single event upsets; Dual well; multiple-node charge collection; pulse quenching; reinforcing charge collection; scaling trends; single event upset reversal (SEUR); soft error; static random access memories (SRAM); triple-well;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2365546

Filename

6957610