• DocumentCode
    44560
  • Title

    An FPGA-based In-Line Accelerator for Memcached

  • Author

    Lavasani, Maysam ; Angepat, Hari ; Chiou, Derek

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
  • Volume
    13
  • Issue
    2
  • fYear
    2014
  • fDate
    July-Dec. 15 2014
  • Firstpage
    57
  • Lastpage
    60
  • Abstract
    We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packets directly from the network, avoiding the CPU in most cases. The accelerator is created by profiling the application to determine the most commonly executed trace of basic blocks which are then extracted. Traces are executed speculatively within the FPGA. If the control flow exits the trace prematurely, the side effects of the computation are rolled back and the request packet is passed to the CPU. When compared to the best reported software numbers, the Memcached accelerator is 9.15× more energy efficient for common case requests.
  • Keywords
    cache storage; distributed processing; field programmable gate arrays; reconfigurable architectures; FPGA-based in-line accelerator; Memcached accelerator; accelerating server; control flow; distributed key-value system; hybrid CPU+FPGA architecture; request packet; rolled back; software numbers; Client-server systems; Computer architecture; Field programmable gate arrays; Hybrid systems; Program processors; C.1.3.f Heterogeneous (hybrid) systems; C.2.4.a Client/server;
  • fLanguage
    English
  • Journal_Title
    Computer Architecture Letters
  • Publisher
    ieee
  • ISSN
    1556-6056
  • Type

    jour

  • DOI
    10.1109/L-CA.2013.17
  • Filename
    6560058