A VLSI architecture for finite ridgelet transform

Author

Rahman, Choudhury A. ; Badawy, Wael

Author_Institution

Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada

Volume

2

fYear

2003

fDate

27-30 Dec. 2003

Firstpage

594

Abstract

This paper presents a VLSI architecture for the finite ridgelet transform (FRIT). The proposed architecture has been partitioned into two stages. First stage computes the finite Radon transform (FRAT) coefficients and the second stage computes 1-D discrete wavelet transform (DWT) coefficients. The simulation result shows that the core speed of the proposed architecture is around 66 MHz and the improvement over direct filter based implementation is 42.97%. The prototype is designed as an IP-block for SOC integration. The proposed architecture is prototyped using Verilog HDL and synthesized by Xilinx ISE development tools. "xc2v3000" device of Virtex-II device family has been used in this synthesis.

Keywords

Radon transforms; VLSI; discrete wavelet transforms; hardware description languages; hardware-software codesign; SOC integration; VLSI architecture; Verilog HDL; Xilinx ISE; discrete wavelet transform; filter; finite Radon transform; finite ridgelet transform; Computational modeling; Computer architecture; Discrete transforms; Discrete wavelet transforms; Hardware design languages; Image restoration; Prototypes; US Department of Transportation; Very large scale integration; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562356

Filename

1562356