An efficient digital downconversion structure with bandwidth matched receiving

In this paper, an efficient digital down-conversion (DDC) structure with bandwidth matched receiving, which is based on rational data rate conversion, is given for matched receiving of signals with arbitrary bandwidth. The structure effectively reduces the great gap between the output data rate of the high-speed ADC and the low processing speed of DSP. It combines the conventional structure of DDC with rational data rate conversion. Signals with variable bandwidth are matched received by controlling the interpolation and decimation factors. Moreover, by utilizing the relationship between anti-imaging and anti-aliasing filtering and the interpolation and decimation factors, only decimated data need to be calculated, which, together with a parallel processing structure, achieves high-speed and efficient filtering. Computer simulations have validated the correctness and validity of the structure.