Verification of Timing Constraints on Large Digital Systems

A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-1 Mark IIA processor.