DocumentCode
450389
Title
Development in Verification of Design Correctness
Author
Cory, W.E. ; vanCleemput, W.M.
Author_Institution
Stanford University, Stanford, CA
fYear
1980
fDate
23-25 June 1980
Firstpage
156
Lastpage
164
Abstract
This paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verfication by grammar construction, comparison of manually generated design with automated design, and functional abstraction.
Keywords
Application software; Computational modeling; Digital systems; Documentation; Hardware design languages; Humans; Permission; System testing; Tiles; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1980. 17th Conference on
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1980.1585242
Filename
1585242
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