An Accurate Functional Level Concurrent Fault Simulator

This paper describes the basic data structures and algorithms for a functional level fault simulator. The technique used is that of concurrent fault simulation. The algorithms and date structure support multi-signal value, gate and functional level device models. These algorithms and data structures also support the capability to simulate user defined faults and faults that cause timing violations. In the experimental version of the system, developed at the University of Texas, only classical stuck-at faults and faults that lead to timing discrepancies between the good and the faulty circuit were implemented. Minor additions to the data structures will allow the simulator to process non-classical faults like: (1) memory stuck-at, (2) user defined functional faults, (3) technology dependent shorted signal faults, etc. The accuracy achieved simulating a fault is consistent with the accuracy of the non-fault model.