VISION: VHDL Induced Schematic Imaging on Net-Lists

This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented.