Title :
Layout Optimization of CMOS Functional Cells
Author :
Maziasz, Robert L. ; Hayes, John P.
Author_Institution :
Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Abstract :
An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and vanCleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.
Keywords :
Algebra; CMOS technology; Delay; Distributed computing; Layout; Logic circuits; MOS devices; Machinery; Semiconductor device modeling; Topology;
Conference_Titel :
Design Automation, 1987. 24th Conference on
Print_ISBN :
0-8186-0781-5
DOI :
10.1109/DAC.1987.203295
