• DocumentCode
    450582
  • Title

    Scheduling High-Level Blocks for Functional Simulation

  • Author

    Wang, Zhicheng ; Maurer, Peter M.

  • Author_Institution
    Department of Computer Science and Engineering, University of South Florida, Tampa, FL
  • fYear
    1989
  • fDate
    25-29 June 1989
  • Firstpage
    87
  • Lastpage
    90
  • Abstract
    This paper presents a method for scheduling high-level blocks for functional simulation under the assumptions that circuits may be cyclic (due to element grouping), and that blocks cannot be broken down into simpler elements. The solution presented here may simulate one block many times per clock period. Obtaining a minimal schedule for a cyclic circuit is shown to be NP-complete, and two approximation algorithms are presented, along with empirical data to evaluate their effectiveness.
  • Keywords
    Algorithms; Circuit simulation; Clocks; Computational modeling; Computer science; Computer simulation; Flip-flops; Permission; Processor scheduling; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1989. 26th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-310-8
  • Type

    conf

  • DOI
    10.1109/DAC.1989.203375
  • Filename
    1586359