Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits

In this paper we investigate two aspects regarding the detection of stuck-open (SOP) faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. The performance of the proposed method is compared with that of a competing method. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.