Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour

This paper discusses the kernel implementation issues of a new and more formal approach to electrical verification. Rule based analysis of the transistor network is applied to derive the signal flow direction and to identify control and state nodes. Symbolic analysis of boolean expressions, capturing all aspects of switch level networks, allows to take into account the logical structure of the network and its environment during verification and guarantees more relevant error reports. The application of the proposed strategy on real life examples, demonstrates its usefulness and allows for a realistic evaluation of the tool.