• DocumentCode
    450669
  • Title

    VHDL Synthesis Using Structured Modeling

  • Author

    Lis, Joseph S. ; Gajski, Daniel D.

  • Author_Institution
    Dept. of Information & Computer Science, University of California, Irvine, Irvine, CA
  • fYear
    1989
  • fDate
    25-29 June 1989
  • Firstpage
    606
  • Lastpage
    609
  • Abstract
    This paper describes the use of VHDL in a behavioral synthesis system. A structured modeling methodology is presented which suggests standard practices for writing VHDL descriptions which span a variety of design models. The VHDL Synthesis System (VSS) processes each of these input descriptions and produces a structural description of generic components.
  • Keywords
    Circuit synthesis; Clocks; Computer science; Logic design; Microarchitecture; Permission; Registers; Timing; Variable structure systems; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1989. 26th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-310-8
  • Type

    conf

  • DOI
    10.1109/DAC.1989.203468
  • Filename
    1586452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=450669