Algorithms for Accuracy Enhancement in a Hardware Logic Simulator

In this paper, we describe a hardware multiple delay logic simulator that incorporates efficient timing analyses algorithms for event cancellations, spike and race analyses and oscillation detection. The algorithms are implemented on a set of reconfigurable processors, arranged in a pipelined configuration. Spike analysis is accomplished by dynamic pulse width measurement. Both zero and non-zero delay oscillations are detected. Results of simulating industrial VLSI chips are presented to illustrate the effectiveness of the algorithms with minimal performance penalty.