• DocumentCode
    450694
  • Title

    CMOS Stuck-Open Fault Detection Using Single Test Patterns

  • Author

    Rajsuman, R. ; Jayasumana, A.P. ; Malaiya, Y.K.

  • Author_Institution
    Department of Computer Engineering, Case Western Reserve University, Cleveland, OH
  • fYear
    1989
  • fDate
    25-29 June 1989
  • Firstpage
    714
  • Lastpage
    717
  • Abstract
    CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMOS or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing.
  • Keywords
    CMOS technology; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Logic testing; Permission; Robustness; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1989. 26th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-310-8
  • Type

    conf

  • DOI
    10.1109/DAC.1989.203493
  • Filename
    1586477