DocumentCode :
450702
Title :
Behavioral Modeling of Transmission Gates in VHDL
Author :
Leung, Steven S.
Author_Institution :
Department of Electrical Engineering, Michigan State University, East Lansing, MI
fYear :
1989
fDate :
25-29 June 1989
Firstpage :
746
Lastpage :
749
Abstract :
This paper presents a technique for describing the behavior of transmission gates (TGs) in VHDL. The concept of virtual signal is introduced into the TG´s data structure to represent the nature of the connection. The model´s semantics are coded in three parts: the state transition, the steady states, and the connecting protocol. Simulation results indicate that the model is correct and robust.
Keywords :
Circuits; Data structures; Hardware; Inverters; Joining processes; Logic functions; Permission; Protocols; Robustness; Steady-state;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1989. 26th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-310-8
Type :
conf
DOI :
10.1109/DAC.1989.203501
Filename :
1586485
Link To Document :
بازگشت