DocumentCode
451091
Title
Performance of the CRAY T3E Multiprocessor
Author
Anderson, Ed ; Brooks, Jeff ; Grassl, Charles ; Scott, Steve
Author_Institution
Cray Research, Inc.
fYear
1997
fDate
15-21 Nov. 1997
Firstpage
39
Lastpage
39
Abstract
The CRAY T3E is a scalable shared-memory multiprocessor based on the DEC Alpha 21164 microprocessor. The system includes a number of architectural features designed to tolerate latency and enhance scalability. Included among these are stream buffers, which detect and prefetch down small-stride reference streams, E-registers, which allow memory reference pipelining and provide non-unit-stride access capabilities, and a scalable, high-bandwidth interconnection network. We report our experiences with T3E performance. We describe several hardware features, discuss programming implications, and provide related benchmark results. Included are NAS Parallel Benchmark results up to 1024 processors.
Keywords
Bandwidth; Clocks; Control systems; Delay; Hardware; Microprocessors; Prefetching; Registers; Scalability; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Supercomputing, ACM/IEEE 1997 Conference
Print_ISBN
0-89791-985-8
Type
conf
DOI
10.1109/SC.1997.10043
Filename
1592620
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