Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Author

Jazaeri, F. ; Barbut, L. ; Sallese, J.-M.

Author_Institution

Swiss Fed. Inst. of Technol. in Lausanne, Lausanne, Switzerland

Volume

61

Issue

12

fYear

2014

fDate

Dec. 2014

Firstpage

3962

Lastpage

3970

Abstract

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent double-gate junctionless architectures, including mismatch in gate capacitance and material work functions.

Keywords

field effect transistors; semiconductor device models; work function; asymmetric operation; double-gate junctionless FET; double-gate junctionless architectures; gate capacitance; symmetric devices; virtual symmetric device; work functions; Analytical models; Electric potential; Field effect transistors; Logic gates; Mathematical model; Accumulation; FET; asymmetric; compact model; double gate (DG); junctionless (JL); nanowire; nanowire.;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2361358

Filename

6960067