Sequential Circuit Test Generation on a Distributed System

A sequential circuit test generation program is parallelized to run on a network of Sparc 2 workstations connected through ethernet. Sixteen processors are served by a single file server. The test generation program uses the time-frame expansion circuit model, and a branch and bound search algorithm in reverse time processing mode. The fault list is equally divided among the processors. The entire process consists of a series of parallel computing passes with synchronization occurring between passes. During a pass, each processor independently generates test sequences for the assigned faults through vector generation and fault simulation. A fixed per-fault CPU time limit is used within a pass. Faults requiring more time are abandoned for later passes. At the end of a pass, each processor simulates the entire fault list with its vectors and transmits the list of undetected faults to all other processors. Processors then combine these fault lists to create a list of faults that were not detected by all processors. This list is again equally divided and the next pass begins with a larger per-fault time limit for test generation. The process stops after either the required fault coverage is achieved or the pass with given maximum per-fault time limit is completed. Some benchmark results are given to show the advantage of distributed system for large circuits. The paper also outlines the lessons learned from the experiment and makes suggestions for improvement.