DocumentCode
451899
Title
A Layout Estimation Algorithm for RTL Datapaths
Author
Nourani, Mehrdad ; Papachristou, Christos
Author_Institution
Department of Computer Engineering, Case Western Reserve University, Cleveland, OH
fYear
1993
fDate
14-18 June 1993
Firstpage
285
Lastpage
291
Abstract
This paper presents a fast and efficient algorithm to estimate the area cost of a given RTL datapath. This is achieved by considering the physical length of components (provided by a component library) and connections data (given by the datapath description) within an actual layout model and using analytical formulas in a constructive algorithm. Our layout estimator uses a non-probabilistic basis to estimate the overall cost of a datapath structure. It can estimate the overall layout with emphasis on area minimization, or can be adapted to delay minimization depending on the user request. Layout area is estimated for Standard-Cell and Full-custom layout methodologies at the RT level.
Keywords
Algorithm design and analysis; Circuit synthesis; Constraint optimization; Costs; Data engineering; Delay estimation; High level synthesis; Libraries; Process design; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.203961
Filename
1600234
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