Iterative Wirability and Performance Improvement for FPGAs

In FPGAs, routing resources are fixed and their usage is constrained by the location of antifuses. This severely limits the ability to make accurate wirability and timing predictions at the placement level. There is a need, therefore, for a layout flow in which an incremental placer changes the layout based on post-layout timing and wirability analysis. In this paper we consider such an incremental placer. Up to 29% improvement in timing has been obtained for a set of industrial designs and MCNC benchmark examples.