DocumentCode
451977
Title
A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design
Author
Cong, Jason ; Smith, M´Lissa
Author_Institution
Department of Computer Science, University of California, Los Angeles, Los Angeles, CA
fYear
1993
fDate
14-18 June 1993
Firstpage
755
Lastpage
760
Abstract
In this paper, we present a bottom-up clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to identify clusters simultaneously. We also present a cluster-based partitioning method in which our clustering algorithm is used as a preprocessing step to both the bisection algorithm by Fiduccia and Mattheyses and a ratio-cut algorithm by Wei and Cheng. Our results show that cluster-based partitioning obtains cut sizes up to 49.6% smaller than the bisection algorithm, and obtains ratio cut sizes up to 66.8% smaller than the ratio-cut algorithm. Moreover, we show that cluster-based partitioning produces much stabler results than direct partitioning.
Keywords
Algorithm design and analysis; Application software; Circuit stability; Clustering algorithms; Computer science; Iterative algorithms; Partitioning algorithms; Terminology; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.204048
Filename
1600321
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