Clock Grouping: A Low Cost DFT Methodology for Delay Testing

A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault coverage for circuits by exercising greater control over flip-flop clocks in the test mode. In the test mode, the flip-flops are partitioned into different clock-groups. The flip-flops in each clock group can be either clocked or not clocked, independent of the flip-flops in the other groups. This exibility is used to enhance the number of different (v₁, v₂) test pairs that can be applied to the state inputs of the circuit thereby increasing coverage of delay faults. Experimental data on benchmark circuits shows that high fault coverage can be obtained by using only two clock groups in most circuits. The proposed clock grouping methodology can be applied to non-scan circuits as well. In fact, it can provide a DFT solution for high speed data path circuits where the performance penalties of conventional DFT techniques are unacceptable.